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| Am41DL3208G Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 25870 Revision A Amendment 0 Issue Date February 13, 2002 PRELIMINARY Am41DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features I Power supply voltage of 2.7 to 3.3 volt I High performance -- Access time as fast as 70 ns -- 10 mA active read current at 5 MHz -- 200 nA in standby or automatic sleep mode I Minimum 1 million write cycles guaranteed per sector I 20 Year data retention at 125C -- Reliable operation for the life of the system I Package -- 73-Ball FBGA I Operating Temperature -- -40C to +85C SOFTWARE FEATURES I Data Management Software (DMS) -- AMD-supplied software manages data programming and erasing, enabling EEPROM emulation -- Eases sector erase limitations Flash Memory Features ARCHITECTURAL ADVANTAGES I Simultaneous Read/Write operations -- Data can be continuously read from one bank while executing erase/program functions in other bank -- Zero latency between read and write operations I Supports Common Flash Memory Interface (CFI) I Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES I Any combination of sectors can be erased I Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion I Flexible BankTM architecture -- Read may occur in any of the three banks not being written or erased. -- Four banks may be grouped by customer to achieve desired bank divisions. I Secured Silicon (SecSi) Sector: Extra 256 Byte sector -- Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. -- Customer lockable: Sector is one-time programmable. Once locked, data cannot be changed I Hardware reset pin (RESET#) -- Hardware method of resetting the internal state machine to reading array data I WP#/ACC input pin -- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status -- Acceleration (ACC) function accelerates program timing I Zero Power Operation -- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero I Sector protection -- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector -- Temporary Sector Unprotect allows changing data in protected sectors in-system I Top or bottom boot block I Manufactured on 0.17 m process technology I Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash standard SRAM Features I Power dissipation -- Operating: 30 mA maximum -- Standby: 15 A maximum PERFORMANCE CHARACTERISTICS I High performance -- Access time as fast as 70 ns -- Program time: 4 s/word typical utilizing Accelerate function I Ultra low power consumption (typical values) -- 2 mA active read current at 1 MHz I I I I CE1s# and CE2s Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 1.5 to 3.3 volt Byte data control: LB#s (DQ7-DQ0), UB#s (DQ15-DQ8) This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 25870 Rev: A Amendment/0 Issue Date: February 13, 2002 Refer to AMD's Website (www.amd.com) for the latest information. PRELIMINARY GENERAL DESCRIPTION Am29DL320G Features The Am29DL320G consists of 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data app e a r s o n D Q 1 5 - D Q 0 ; b yt e m o d e d a t a a p p e a r s o n DQ7-DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The devices are available with access times of 70 and 85 ns. The device is offered in a 73-ball FBGA package. Standard control pins--chip enable (CE#f), write enable (WE#), and output enable (OE#)--control normal read and write operations, and avoid bus contention issues. The devices requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. some previous AMD 32 Mbit Am29DL32x devices had a larger SecSi Sector. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD's ExpressFlash service), or both. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory devi c e (o r m e m o ry d e vi c e s ) , a n d m o r e . U s i n g D M S , user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses t he F lash memo ry b y callin g one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 4 Mb banks with small and large sectors, and two 12 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device allows a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL320G can be organized as either a top or bottom boot sector configuration. Bank Bank 1 Bank 2 Bank 3 Bank 4 Megabits 4 Mb 12 Mb 12 Mb 4 Mb Sector Sizes Eight 8 Kbyte/4 Kword, Seven 64 Kbyte/32 Kword Twenty-four 64 Kbyte/32 Kword Twenty-four 64 Kbyte/32 Kword Eight 64 Kbyte/32 Kword Am41DL3208G Features The SecSi TM (Secured Silicon) Sector is an 256 byte extra sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Note that 2 Am41DL3208G February 13, 2002 PRELIMINARY TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Handling Instructions for FBGA Package .................... 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10 Table 1. Device Bus Operations--Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC ..................................................... 11 Table 2. Device Bus Operations--Flash Word Mode, CIOf = VIH; SRAM Byte Mode, CIOs = VSS ......................................................12 Table 3. Device Bus Operations--Flash Byte Mode, CIOf = VSS; SRAM Word Mode, CIOs = VCC .....................................................13 Table 4. Device Bus Operations--Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS ..................................................................14 Reset Command ..................................................................... 28 Autoselect Command Sequence ............................................ 28 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 29 Byte/Word Program Command Sequence ............................. 29 Unlock Bypass Command Sequence .................................. 29 Figure 3. Program Operation ......................................................... 30 Chip Erase Command Sequence ........................................... 30 Sector Erase Command Sequence ........................................ 30 Erase Suspend/Erase Resume Commands ........................... 31 Figure 4. Erase Operation.............................................................. 31 Table 15. Command Definitions (Flash Word Mode) ...................... 32 Table 16. Command Definitions (Flash Byte Mode) ....................... 33 Write Operation Status . . . . . . . . . . . . . . . . . . . . 34 DQ7: Data# Polling ................................................................. 34 Figure 5. Data# Polling Algorithm .................................................. 34 Word/Byte Configuration ........................................................ 15 Requirements for Reading Array Data ................................... 15 Writing Commands/Command Sequences ............................ 15 Accelerated Program Operation .......................................... 15 Autoselect Functions ........................................................... 15 Simultaneous Read/Write Operations with Zero Latency ....... 15 Standby Mode ........................................................................ 16 Automatic Sleep Mode ........................................................... 16 RESET#: Hardware Reset Pin ............................................... 16 Output Disable Mode .............................................................. 16 Table 5. Device Bank Division ........................................................16 Table 6. Top Boot Sector Addresses .............................................17 Top Boot SecSi Sector Addresses ............................................. 18 Table 8. Bottom Boot Sector Addresses .........................................19 Bottom Boot SecSi Sector Addresses ........................................ 20 RY/BY#: Ready/Busy# ............................................................ 35 DQ6: Toggle Bit I .................................................................... 35 Figure 6. Toggle Bit Algorithm........................................................ 35 DQ2: Toggle Bit II ................................................................... 36 Reading Toggle Bits DQ6/DQ2 ............................................... 36 DQ5: Exceeded Timing Limits ................................................ 36 DQ3: Sector Erase Timer ....................................................... 36 Table 17. Write Operation Status ................................................... 37 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 38 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 38 Industrial (I) Devices ............................................................ 38 VCCf/VCC s Supply Voltage ................................................... 38 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 CMOS Compatible .................................................................. 39 SRAM DC and Operating Characteristics . . . . . 40 Zero-Power Flash ................................................................. 41 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ........................................................................................ 41 Figure 10. Typical ICC1 vs. Frequency ............................................ 41 Autoselect Mode ..................................................................... 21 Sector/Sector Block Protection and Unprotection .................. 21 Table 10. Top Boot Sector/Sector Block Addresses for Protection/Unprotection .............................................................21 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 11. Test Setup.................................................................... 42 Table 18. Test Specifications ......................................................... 42 Write Protect (WP#) ................................................................ 21 Temporary Sector/Sector Block Unprotect ............................. 22 Figure 1. Temporary Sector Unprotect Operation........................... 22 Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms .............................................................................................. 23 Key To Switching Waveforms . . . . . . . . . . . . . . . 42 Figure 12. Input Waveforms and Measurement Levels ................. 42 SecSi (Secured Silicon) Sector Flash Memory Region .......... 24 Factory Locked: SecSi Sector Programmed and Protected At the Factory .......................................................................... 24 Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory ........................................................... 24 Hardware Data Protection ...................................................... 24 Low VCC Write Inhibit ........................................................... 24 Write Pulse "Glitch" Protection ............................................ 24 Logical Inhibit ...................................................................... 24 Power-Up Write Inhibit ......................................................... 25 Common Flash Memory Interface (CFI) . . . . . . . 25 Table 11. CFI Query Identification String ........................................ 25 System Interface String................................................................... 26 Table 13. Device Geometry Definition ............................................ 26 Table 14. Primary Vendor-Specific Extended Query ...................... 27 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43 SRAM CE#s Timing ................................................................ 43 Figure 13. Timing Diagram for Alternating Between SRAM to Flash .. 43 Flash Read-Only Operations ................................................. 44 Figure 14. Read Operation Timings ............................................... 44 Hardware Reset (RESET#) .................................................... 45 Figure 15. Reset Timings ............................................................... 45 Flash Word/Byte Configuration (CIOf) .................................... 46 Figure 16. CIOf Timings for Read Operations................................ 46 Figure 17. CIOf Timings for Write Operations................................ 46 Flash Erase and Program Operations .................................... 47 Figure 18. Program Operation Timings.......................................... Figure 19. Accelerated Program Timing Diagram.......................... Figure 20. Chip/Sector Erase Operation Timings .......................... Figure 21. Back-to-back Read/Write Cycle Timings ...................... Figure 22. Data# Polling Timings (During Embedded Algorithms). Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... Figure 24. DQ2 vs. DQ6................................................................. 48 48 49 50 50 51 51 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 28 Reading Array Data ................................................................ 28 February 13, 2002 Am41DL3208G 3 PRELIMINARY Temporary Sector/Sector Block Unprotect ............................. 52 Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram............................................................................... 52 Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram............................................................................... 53 Figure 32. SRAM Write Cycle--UB#s and LB#s Control ............... 60 Alternate CE#f Controlled Erase and Program Operations .... 54 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings................................................................................ 55 Flash Erase And Programming Performance ........................ 61 Flash Latchup Characteristics. . . . . . . . . . . . . . . 61 Package Pin Capacitance . . . . . . . . . . . . . . . . . . 61 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 61 SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 62 Figure 33. CE1#s Controlled Data Retention Mode....................... 62 Figure 34. CE2s Controlled Data Retention Mode......................... 62 SRAM Read Cycle .................................................................. 56 Figure 28. SRAM Read Cycle--Address Controlled....................... 56 Figure 29. SRAM Read Cycle ......................................................... 57 SRAM Write Cycle .................................................................. 58 Figure 30. SRAM Write Cycle--WE# Control ................................. 58 Figure 31. SRAM Write Cycle--CE1#s Control .............................. 59 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63 FLB073--73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 63 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 64 Revision A (January 3, 2002) ................................................. 64 4 Am41DL3208G February 13, 2002 PRELIMINARY PRODUCT SELECTOR GUIDE Part Number Speed Options Standard Voltage Range: VCC = 2.7-3.3 V Flash Memory 70 70 70 30 85 85 85 40 70 70 70 35 Am41DL3208G SRAM 85 85 85 45 Max Access Time (ns) CE# Access (ns) OE# Access (ns) MCP BLOCK DIAGRAM VCCf A20 to A0 A20 to A0 A-1 WP#/ACC RESET# CE#f CIOf VSS RY/BY# 32 M Bit Flash Memory DQ15/A-1 to DQ0 DQ15/A-1 to DQ0 VCCs/VCCQ VSS/VSSQ A0 toto A0 A18 A19 SA LB#s UB#s WE# OE# CE1#s CE2s CIOs 8 M Bit Static RAM DQ15/A-1 to DQ0 February 13, 2002 Am41DL3208G 5 PRELIMINARY FLASH MEMORY BLOCK DIAGRAM VCC VSS OE# CIOf Y-Decoder A20-A0 Upper Bank Address Upper Bank Latches and Control Logic RY/BY# A20-A0 RESET# WE# CE# CIOf WP#/ACC DQ15-DQ0 A20-A0 STATE CONTROL & COMMAND REGISTER X-Decoder Status DQ15-DQ0 Control DQ15-DQ0 X-Decoder Lower Bank A20-A0 Lower Bank Address OE# 6 Am41DL3208G Latches and Control Logic Y-Decoder CIOf DQ15-DQ0 A20-A0 February 13, 2002 PRELIMINARY CONNECTION DIAGRAM 73-Ball FBGA Top View A1 NC A10 NC Flash only B1 NC B5 NC B6 NC B10 NC SRAM only C1 NC C3 A7 C4 D4 UB# C5 D5 E5 RY/BY# C6 D6 E6 A20 C7 A8 C8 A11 Shared LB# WP#/ACC WE# D2 A3 D3 A6 D7 A19 D8 A12 D9 A15 RESET# CE2s E2 A2 E3 A5 E4 A18 E7 A9 E8 A13 E9 NC F1 NC F2 A1 F3 A4 F4 A17 F7 A10 F8 A14 F9 NC F10 NC G1 NC G2 A0 G3 VSS G4 DQ1 G7 DQ6 G8 SA G9 A16 G10 NC H2 CE#f H3 OE# H4 DQ9 H5 DQ3 H6 DQ4 H7 J7 DQ12 H8 J8 DQ7 H9 J9 VSS DQ13 DQ15/A-1 CIOf J2 CE1#s J3 DQ0 J4 DQ10 J5 VCCf J6 VCCs K3 DQ8 K4 DQ2 K5 DQ11 K6 CIOs K7 DQ5 K8 DQ14 L1 NC L5 NC L6 NC L10 NC M1 NC M10 NC Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. February 13, 2002 Am41DL3208G 7 PRELIMINARY PIN DESCRIPTION A18-A0 = 19 Address Inputs (Common) A-1, A20-A19 = 3 Address Inputs (Flash) SA DQ15-DQ0 CE#f CE#s OE# WE# RY/BY# UB#s LB#s CIOf = Highest Order Address Pin (SRAM) Byte mode = 16 Data Inputs/Outputs (Common) = Chip Enable (Flash) = Chip Enable (SRAM) = Output Enable (Common) = Write Enable (Common) = Ready/Busy Output = Upper Byte Control (SRAM) = Lower Byte Control (SRAM) = I/O Configuration (Flash) CIOf = VIH = Word mode (x16), CIOf = VIL = Byte mode (x8) = I/O Configuration (SRAM) CIOs = VIH = Word mode (x16), CIOs = VIL = Byte mode (x8) = Hardware Reset Pin, Active Low = Hardware Write Protect/ Acceleration Pin (Flash) = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = SRAM Power Supply = Device Ground (Common) = Pin Not Connected Internally LOGIC SYMBOL 19 A18-A0 A-1, A20-A19 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf CIOs RY/BY# DQ15-DQ0 16 or 8 CIOs RESET# WP#/ACC VCCf VCCs VSS NC 8 Am41DL3208G February 13, 2002 PRELIMINARY ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am41DL320 8 G T 70 I T TAPE AND REEL T = 7 inches TEMPERATURE RANGE I = Industrial (-40C to +85C) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector PROCESS TECHNOLOGY G = 0.17 m SRAM DEVICE DENSITY 8 = 8 Mbits AMD DEVICE NUMBER/DESCRIPTION Am41DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL320G 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM Valid Combinations Order Number Am41DL3208GT70I AM41DL3208GB70I T Am41DL3208GT85I Am41DL3208GB85I M41000003F M41000003G Package Marking M41000003D M41000003E Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations February 13, 2002 Am41DL3208G 9 PRELIMINARY DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory locat io n. Th e re g ist e r is a la t ch u se d t o st or e t h e commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1 through 3 list the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. 10 Am41DL3208G February 13, 2002 PRELIMINARY Table 1. Operation (Notes 1, 2) Read from Flash Device Bus Operations--Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC CE#f CE1#s CE2s OE# WE# L H X H X H X L H X H X L X L X L H X L X L X L X L H L X H L X L H SA X Addr. AIN AIN X X X X SADD, A6 = L, A1 = H, A0 = L SADD, A6 = H, A1 = H, A0 = L X LB#s UB#s RESET# X X H WP#/ACC DQ7- (Note 4) DQ0 L/H DOUT DIN High-Z DQ15- DQ8 DOUT DIN High-Z Write to Flash L VCC 0.3 V L H L X X X H VCC 0.3 V H (Note 4) Standby X H H X X H H X X X X X X L X X X X L X H Output Disable Flash Hardware Reset Sector Protect (Note 5) L/H High-Z High-Z X L L/H High-Z High-Z L X H X X VID L/H DIN X Sector Unprotect (Note 5) Temporary Sector Unprotect L X H X X X VID (Note 6) DIN X X X X X X L X L L H L L H VID (Note 6) DIN DOUT High-Z DOUT DOUT High-Z DIN DIN High-Z Read from SRAM H L H L H X AIN H L L H X High-Z DOUT DIN Write to SRAM H L H X L X AIN H L H X High-Z DIN Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 9.0 0.5 V, X = Don't Care, SA = SRAM Address Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don't care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector/Sector Block Protection and Unprotection" section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP#/ACC = VHH, all sectors will be unprotected. February 13, 2002 Am41DL3208G 11 PRELIMINARY Table 2. Device Bus Operations--Flash Word Mode, CIOf = VIH; SRAM Byte Mode, CIOs = VSS Operation (Notes 1, 2) Read from Flash CE#f CE1#s CE2s OE# WE# SA L H X H X H X L H X H Sector Protect (Note 5) L X H Sector Unprotect (Note 5) Temporary Sector Unprotect Read from SRAM Write to SRAM L X H X L L X L X L X L H X L X L X L X L H H H L X H L X L H X Addr. AIN AIN X X X SADD, A6 = L, A1 = H, A0 = L SADD, A6 = H, A1 = H, A0 = L AIN AIN AIN LB#s UB#s WP#/ACC DQ7- DQ15- RESET# (Note 4) DQ0 DQ8 (Note 3) (Note 3) X X H L/H DOUT DIN DOUT DIN Write to Flash L VCC 0.3 V L X H L X X X H VCC 0.3 V H L (Note 3) Standby Output Disable Flash Hardware Reset X H X X H X X SA X X DNU X X DNU X H L/H L/H High-Z High-Z High-Z High-Z High-Z High-Z X X VID L/H DIN X X X VID (Note 6) DIN X X H H X L X X H L X SA SA X X X X X X VID H H (Note 6) X X DIN DOUT DIN High-Z High-Z High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 9.0 0.5 V, X = Don't Care, SA = SRAM Address Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out, DNU = Do Not Use Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don't care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector/Sector Block Protection and Unprotection" section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP#/ACC = VHH, all sectors will be unprotected. 12 Am41DL3208G February 13, 2002 PRELIMINARY Table 3. Operation (Notes 1, 2) Read from Flash Device Bus Operations--Flash Byte Mode, CIOf = VSS; SRAM Word Mode, CIOs = VCC CE#f CE1#s CE2s OE# WE# SA L H X H X H X L H X H X L X L X L H X L X L X L x L X X X AIN X L X L L H L L H H X H X VID (Note 6) DIN DOUT High-Z DOUT DIN High-Z DIN High-Z DOUT DOUT High-Z DIN DIN High-Z H L X H L X L H X Addr. AIN AIN X LB#s UB#s WP#/ACC RESET# (Note 3) (Note 3) (Note 4) X X H L/H DQ7- DQ0 DOUT DIN High-Z DQ15- DQ8 High-Z Write to Flash L VCC 0.3 V L H L X X X H VCC 0.3 V H (Note 3) High-Z Standby X X X X L X X X X L X H High-Z Output Disable Flash Hardware Reset Sector Protect (Note 5) H H X X L/H High-Z High-Z X X X X X SADD, A6 = L, A1 = H, A0 = L SADD, A6 = L, A1 = H, A0 = L L L/H High-Z High-Z L X H X X VID L/H DIN X Sector Unprotect (Note 5) Temporary Sector Unprotect Read from SRAM L X H X X VID (Note 6) DIN X X X H L H L H X AIN H L L Write to SRAM H L H X L X AIN H L Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 9.0 0.5 V, X = Don't Care, SA = SRAM Address Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don't care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector/Sector Block Protection and Unprotection" section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP#/ACC = VHH, all sectors will be unprotected. February 13, 2002 Am41DL3208G 13 PRELIMINARY Table 4. Operation (Notes 1, 2) Read from Flash Device Bus Operations--Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS CE#f CE1#s CE2s OE# WE# L H X H X H X L H X H X L X L X L H X L X L X L X L H H H L X H L X L H SA X Addr. AIN AIN X X X SADD, A6 = L, A1 = H, A0 = L SADD, A6 = L, A1 = H, A0 = L AIN AIN AIN LB#s UB#s WP#/ACC RESET# (Note 3) (Note 3) (Note 4) X X H L/H DQ7- DQ0 DOUT DIN High-Z High-Z High-Z DQ15- DQ8 High-Z Write to Flash L VCC 0.3 V H X H L X X X H VCC 0.3 V H L (Note 3) High-Z Standby Output Disable Flash Hardware Reset Sector Protect (Note 5) X H X X H X X SA X X DNU X X DNU X H L/H L/H High-Z High-Z High-Z L X H X X VID L/H DIN X Sector Unprotect (Note 5) Temporary Sector Unprotect Read from SRAM Write to SRAM L X H X L L X X VID (Note 6) DIN X X H H X L X X H L X SA SA X X X X X X VID H H (Note 6) X X DIN DOUT DIN High-Z High-Z High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 9.0 0.5 V, X = Don't Care, SA = SRAM Address Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT = Data Out, DNU = Do Not Use Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don't care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector/Sector Block Protection and Unprotection". 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP#/ACC = VHH, all sectors will be unprotected. 14 Am41DL3208G February 13, 2002 PRELIMINARY Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic `1', the device is in word configuration, DQ15-DQ0 are active and controlled by CE# and OE#. If the CIOf pin is set at logic `0', the device is in byte configuration, and only data I/O pins DQ7-DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ14-DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 6-8 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "sector address" is the address bits required to uniquely select a sector. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to VIL. CE#f is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V I H . The CIOf pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See "Requirements for Reading Array Data" for more information. Refer to the AC Flash Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to VIL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to "Word/Byte Configuration" for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Word/Byte Configuration" section has details on programming data to the device using both standard and Unlock Bypass command sequences. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the sam e bank (except the sector b eing erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-program and read-while-erase, respectively. February 13, 2002 Am41DL3208G 15 PRELIMINARY Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than V IH .) If CE#f and RESET# are held at V IH , but not within V CC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS 0.3 V, the device draws CMOS standby current (ICC4 ). If RESET# is held at V IL but not within VSS 0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus mon itor RY/BY# to de term ine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard add r e ss a cce s s t im in g s p ro v id e n e w d a t a w h e n addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 5. Device Bank Division Bank Bank 1 Bank 2 Bank 3 Bank 4 Megabits 4 Mb 12 Mb 12 Mb 4 Mb Sector Sizes Eight 8 Kbyte/4 Kword, Seven 64 Kbyte/32 Kword Twenty-four 64 Kbyte/32 Kword Twenty-four 64 Kbyte/32 Kword Eight 64 Kbyte/32 Kword RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was 16 Am41DL3208G February 13, 2002 PRELIMINARY Table 6. Am29DL320GT Top Boot Sector Addresses Sector Sector Address A20-A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA0 SA1 SA2 Bank 4 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Bank 3 000000xxx 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Bank 2 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 February 13, 2002 Am41DL3208G 17 PRELIMINARY Table 6. Am29DL320GT Top Boot Sector Addresses (Continued) Sector Sector Address A20-A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA48 Bank 2 (continued) SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 Bank 1 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3F1FFFh 3F2000h-3F3FFFh 3F4000h-3F5FFFh 3F6000h-3F7FFFh 3F8000h-3F9FFFh 3FA000h-3FBFFFh 3FC000h-3FDFFFh 3FE000h-3FFFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). The bank address bits are A20-A18. Table 7. Device Am29DL320GT Top Boot SecSi Sector Addresses Sector Address A20-A12 111111xxx Sector Size (Bytes/Words) 256/128 (x8) Address Range 3FE000h-3FE0FFh (x16) Address Range 1F0000h-1FF07Fh 18 Am41DL3208G February 13, 2002 PRELIMINARY Table 8. Am29DL320GB Bottom Boot Sector Addresses Sector Sector Address A20-A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA0 SA1 SA2 SA3 SA4 SA5 Bank 1 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 Bank 2 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 Bank 3 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh SA41 SA42 SA43 SA44 SA45 February 13, 2002 Am41DL3208G 19 PRELIMINARY Table 8. Bottom Boot Sector Addresses (Continued) Am29DL320GB Sector Sector Address A20-A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA46 SA47 SA48 SA49 SA50 SA51 Bank 3 (continued) 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 111000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111xxx 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 Bank 4 SA66 SA67 SA68 SA69 SA70 Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). The bank address bits are A20-A18. Table 9. Device Am29DL320GB Bottom Boot SecSi Sector Addresses Sector Address A20-A12 000000xxx Sector Size (Bytes/Words) 256/128 (x8) Address Range 000000h-0000FFh (x16) Address Range 00000h-00007Fh 20 Am41DL3208G February 13, 2002 PRELIMINARY Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Tables 15 and 16. This method does not require VID . Refer to the Autoselect Command Sequence section for more information. Sector SA67 SA68 SA69 SA70 A20-A12 111111100 111111101 111111110 111111111 Sector/ Sector Block Size 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 10). Table 10. Top Boot Sector/Sector Block Addresses for Protection/Unprotection Sector SA0 SA1-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 SA64 SA65 SA66 A20-A12 000000XXX 000001XXX, 000010XXX 000011XXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX, 111101XXX, 111110XXX 111111000 111111001 111111010 111111011 Sector/ Sector Block Size 64 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (4x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector un protect function is available. See "Temporary Sector/Sector Block Unprotect". Sector protection and unprotection can be implemented as follows. Sector protection and unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 26 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using V ID. This function is one of two provided by the WP#/ACC pin. If the system asserts V IL on the WP#/ACC pin, the device disables program and erase functions in the two "outermost" 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a top-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". February 13, 2002 Am41DL3208G 21 PRELIMINARY Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Temporary Sector/Sector Block Unprotect (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 10). This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID (11.5 V - 12.5 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timing diagrams, for this feature. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation 22 Am41DL3208G February 13, 2002 PRELIMINARY START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 1 s Temporary Sector Unprotect Mode No First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Temporary Sector Unprotect Mode Increment PLSCNT Reset PLSCNT = 1 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 No No PLSCNT = 25? Yes Data = 01h? Increment PLSCNT Yes No Yes No Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address Device failed Protect another sector? No Remove VID from RESET# PLSCNT = 1000? Yes Data = 00h? Yes Device failed Write reset command Last sector verified? Yes No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Note: The term "sector" in the figure applies to both sectors and sector blocks. Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms February 13, 2002 Am41DL3208G 23 PRELIMINARY SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector uses a SecSi Sector Indicator Bit to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either f a cto ry lo cked o r cu sto m e r lo cka b le. Th e f a ctory-locked version is always protected when shipped from the factory, and has the SecSi Sector Indicator Bit permanently set to a "1." The customer-lockable version is shipped with the unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi Sector Indicator Bit permanently set to a "0." Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see "Enter SecSi Sector/Exit SecSi Sector Command Sequence"). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with a random, secure ESN only. In the Top Boot device the ESN will be at addresses 1FF000h-1FF007h in word mode (or addresses 3FE000h-3FE00Fh in byte mode). Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array. The SecSi Sector can be read any number of times, but can be programmed and locked only once, and cannot be erased. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: I Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. I Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the "Sector/Sector Block Protection and Unprotection". Once the SecSi Sector is locked and verified, the syste m m u st w rit e t h e E xit S e cSi S e c to r R e g io n command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 15 and 16 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When V CC is less than VLKO, the device does not accept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f = VIH or WE# = V IH. To initiate a write cycle, 24 Am41DL3208G February 13, 2002 PRELIMINARY CE#f and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE#f = VIL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 11-14. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 11-14. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide We b at ht tp: //ww w. am d.co m/ prod ucts/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Table 11. Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h CFI Query Identification String Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) February 13, 2002 Am41DL3208G 25 PRELIMINARY Table 12. Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h System Interface String Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2 N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2 N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) Table 13. Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0016h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Device Geometry Definition Description Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information 26 Am41DL3208G February 13, 2002 PRELIMINARY Table 14. Addresses (Word Mode) 40h 41h 42h 43h 44h Addresses (Byte Mode) 80h 82h 84h 86h 88h Primary Vendor-Specific Extended Query Description Data 0050h 0052h 0049h 0031h 0033h Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 45h 8Ah 0004h 46h 47h 48h 49h 4Ah 4Bh 4Ch 8Ch 8Eh 90h 92h 94h 96h 98h 0002h 0001h 0001h 0004h 0038h 0000h 0000h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, 38 = Number of Sectors Excluding Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device 4Dh 9Ah 0085h 4Eh 9Ch 0095h 4Fh 9Eh 000Xh February 13, 2002 Am41DL3208G 27 PRELIMINARY COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Tables 15 and 16 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever happens first. Refer to the AC Characteristics section for timing diagrams. which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset co m m a nd r et u rn s t h a t ba n k t o t he e r as e -su sp e n d - re a d m o d e . O n c e p r o g r a m m in g b e g i n s, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to reading array data (or erase-suspend-read mode if that bank was in Erase Suspend). Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, t he co rresp on din g ba n k e nt ers th e era se-su spend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Tables 15 and 16 show the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the auto s e le c t co m m a n d . T h e b a n k t h e n e n t e r s t h e autoselect mode. The system may read at any address within the same bank any number of times witho ut initiating ano ther a utosele ct co mm and sequence: I A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. I A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. I A read cycle to an address containing a sector address (SA) within the same bank, and the address 02h on A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Tables 6-8 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to 28 Am41DL3208G February 13, 2002 PRELIMINARY Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 15 and 16 show the address and data requirements for both command sequences. See also "SecSi (Secured Silicon) Sector Flash Memory Region" for further information. Note that a hardware reset (RESET#=VIL) will reset the device to reading array data. ful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 15 and 16 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the reading array data. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program opera tio n . R e f e r to th e Fla s h E r a se a n d P r o g ra m Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the CIOf pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 15 and 16 show the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- February 13, 2002 Am41DL3208G 29 PRELIMINARY Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Flash Erase and Program Operations tables in the AC Characteristics section for pa ra m e t e rs, an d Fig u re 2 0 se ct ion f o r tim in g diagrams. START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Tables 15 and 16 show the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase addre ss and comm and followin g the e xceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than S e c to r E r a s e o r E r a s e S u s p e nd du r i ng th e time-out period resets that bank to reading array data. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note: Seefor program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Tables 15 and 16 show the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. 30 Am41DL3208G February 13, 2002 PRELIMINARY termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Flash Erase and Progr am Operations tables in the AC Characteristics section for p a ra m e te r s, a n d Fig u re 2 0 s ec tio n f or tim in g diagrams. mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See Tables 15 and 16 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation February 13, 2002 Am41DL3208G 31 PRELIMINARY Table 15. Command Sequence (Note 1) Read (Note 6) Autoselect (Note 8) Reset (Note 7) Manufacturer ID Device ID (Note 9) SecSi Sector Factory Protect (Note 10) Sector Protect Verify (Note 11) Cycles First Addr RA XXX 555 555 555 555 555 555 555 555 XXX BA 555 555 BA BA 55 Data RD F0 AA AA AA AA AA AA AA AA A0 90 AA AA B0 30 98 PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SADD = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20-A12 uniquely select any sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Command Definitions (Flash Word Mode) Bus Cycles (Notes 2-5) Second Addr Data Third Addr Data Addr Fourth Data Fifth Addr Data Sixth Addr Data 1 1 4 4 4 4 3 4 4 3 2 2 6 6 1 1 1 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA PA XXX 2AA 2AA 55 55 55 55 55 55 55 55 PD 00 55 55 (BA)555 (BA)555 (BA)555 (BA)555 555 555 555 555 90 90 90 90 88 90 A0 20 (BA)X00 (BA)X01 (BA)X03 (SADD) X02 XXX PA 0001 7E 0082/0002 0000/0001 (BA) 0E 0A (BA) 0F 0000/ 0001 Enter SecSi Sector Region Exit SecSi Sector Region Program Unlock Bypass Unlock Bypass Program (Note 12) Unlock Bypass Reset (Note 13) Chip Erase Sector Erase Erase Suspend (Note 14) Erase Resume (Note 15) CFI Query (Note 16) 00 PD 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SADD 10 30 Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE#f pulse, whichever happens later. Notes: 1. See Table 1 for description of bus operations. 9. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A20-A12 are don't cares. 6. No unlock or command cycles required when bank is in read mode. 7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. See the Autoselect Command Sequence section for more information. The device ID must be read across three cycles. The device ID is 00h for top boot and 01h for bottom boot. 10. The data is 80h for factory locked and 00h for not factory locked. 11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. 32 Am41DL3208G February 13, 2002 PRELIMINARY Table 16. Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID (Note 9) SecSi Sector Factory Protect (Note 10) Sector Protect Verify (Note 11) Command Definitions (Flash Byte Mode) Bus Cycles (Notes 2-5) Second Addr Data Third Addr Data Fourth Addr Data Fifth Sixth Addr Data Addr Data Cycles 1 1 4 6 4 4 3 4 4 3 2 2 6 6 1 1 1 First Addr Data RA XXX AAA AAA AAA AAA AAA AAA AAA AAA XXX XXX AAA AAA BA BA 55 RD F0 AA AA AA AA AA AA AA AA A0 90 AA AA B0 30 98 555 555 555 555 555 555 555 555 PA XXX 555 555 55 55 55 55 55 55 55 55 PD 00 55 55 (BA) AAA (BA) AAA (BA) AAA (BA) AAA AAA AAA AAA AAA 90 90 90 90 88 90 A0 20 (BA) 00 (BA) 02 (BA) X06 (SADD) X04 XXX PA 01 7E (BA) 1C 0A (BA) 1E 00/01 82/02 00 01 00 PD Enter SecSi Sector Region Exit SecSi Sector Region Program Unlock Bypass Unlock Bypass Program (Note 12) Unlock Bypass Reset (Note 13) Chip Erase Sector Erase Erase Suspend (Note 14) Erase Resume (Note 15) CFI Query (Note 16) AAA AAA 80 80 AAA AAA AA AA 555 555 55 55 AAA SADD 10 30 Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE#f pulse, whichever happens later. Notes: 1. See Table 1 for description of bus operations. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SADD = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20-A12 uniquely select any sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. 9. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A20-A12 are don't cares. 6. No unlock or command cycles required when bank is in read mode. 7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15-DQ8 are don't care. See the Autoselect Command Sequence section for more information. The device ID must be read across three cycles. The device ID is 00h for top boot and 01h for bottom boot. 10. The data is 80h for factory locked and 00h for not factory locked. 11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. February 13, 2002 Am41DL3208G 33 PRELIMINARY WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 17 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. pleted the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-DQ0 will appear on successive read cycles. Table 17 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 22 in the AC Characteristics section shows the Data# Polling timing diagram. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host syst e m wh e t h er an E m b e d d e d P r o gr am o r E ra se algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the bank returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has comSTART Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm 34 Am41DL3208G February 13, 2002 PRELIMINARY RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is reading array data, the standby mo de, or on e of the banks is in the erase-suspend-read mode. Table 17 shows the outputs for RY/BY#. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 17 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 23 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 24 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. START Read DQ7-DQ0 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#f to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determ ine whethe r a sector is active ly erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. Read DQ7-DQ0 Toggle Bit = Toggle? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Twice Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm February 13, 2002 Am41DL3208G 35 PRELIMINARY DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE#f to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 17 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 23 shows the toggle bit timing diagram. Figure 24 shows the differences between DQ2 and DQ6 in graphical form. cles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to reading array data (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 17 shows the status of DQ3 relative to the other status bits. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- 36 Am41DL3208G February 13, 2002 PRELIMINARY Table 17. Status Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program Write Operation Status DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. February 13, 2002 Am41DL3208G 37 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -55C to +125C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -40C to +85C Voltage with Respect to Ground VCCf/VCCs (Note 1) . . . . . . . . . . . . -0.3 V to +4.0 V RESET# (Note 2) . . . . . . . . . . . .-0.5 V to +12.5 V WP#/ACC . . . . . . . . . . . . . . . . . .-0.5 V to +10.5 V All other pins (Note 1) . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O p in s may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 7. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins OE#, RESET#, and WP#/ACC is -0.5 V. During voltage transitions, OE#, WP#/ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of t he device to absolut e maximum rat ing conditions for extended periods may affect device reliability. OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . .-40C to +85C VCCf/VCCs Supply Voltage VCCf/VCCs for standard voltage range . . 2.7 V to 3.3 V Operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns +0.8 V -0.5 V -2.0 V 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 20 ns 20 ns Figure 7. Maximum Negative Overshoot Waveform Figure 8. Maximum Positive Overshoot Waveform 38 Am41DL3208G February 13, 2002 PRELIMINARY DC CHARACTERISTICS CMOS Compatible Parameter Symbol ILI ILIT ILO ILIA Parameter Description Input Load Current RESET# Input Load Current Output Leakage Current ACC Input Leakage Current Test Conditions VIN = VSS to VCC, VCC = V CC max VCC = V CC max; RESET# = 12.5 V VOUT = VSS to VCC, VCC = V CC max VCC = V CC max, WP#/ACC = VACC max CE#f = V IL, OE# = VIH, Byte Mode CE#f = VIL, OE# = VIH, Word Mode 5 MHz 1 MHz 5 MHz 1 MHz 10 2 10 2 15 0.2 0.2 0.2 21 21 21 21 17 ACC pin CE#f = VIL, OE# = VIH VCC pin -0.2 2.4 8.5 5 15 Min Typ Max 1.0 35 1.0 35 16 4 mA 16 4 30 5 5 5 45 mA Word Byte CE#f = VIL, OE# = VIH Word 45 45 mA 45 35 10 30 0.8 VCC + 0.2 9.5 mA mA mA V V V mA A A A Unit A A A A ICC1f Flash VCC Active Read Current (Notes 1, 2) ICC2f ICC3f ICC4f ICC5f Flash VCC Active Write Current (Notes 2, 3) Flash VCC Standby Current (Note 2) Flash VCC Reset Current (Note 2) Flash VCC Current Automatic Sleep Mode (Notes 2, 4) CE#f = VIL, OE# = VIH, WE# = VIL VCCf = VCC max, CE#f, RESET#, WP#/ACC = VCC f 0.3 V VCCf = VCC max, RESET# = VSS 0.3 V, WP#/ACC = VCCf 0.3 V VCCf = VCC max, VIH = VCC 0.3 V; VIL = VSS 0.3 V Byte ICC6f Flash VCC Active Read-While-Program Current (Notes CE#f = VIL, OE# = V IH 1, 2) Flash VCC Active Read-While-Erase Current (Notes 1, 2) Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) ACC Accelerated Program Current, Word or Byte Input Low Voltage Input High Voltage Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect Output Low Voltage ICC7f ICC8f CE#f = VIL, OE#f = VIH IACC VIL VIH VHH VID 11.5 IOL = 4.0 mA, VCCf = VCCs = VCC min IOH = -2.0 mA, VCCf = VCC s = VCC min IOH = -100 A, VCC = VCC min 0.85 x VCC VCC -0.4 2.3 12.5 V VOL VOH1 VOH2 VLKO 0.45 V Output High Voltage Flash Low VCC Lock-Out Voltage (Note 5) V 2.5 V February 13, 2002 Am41DL3208G 39 PRELIMINARY Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol ILI ILO ICC Parameter Description Input Leakage Current Output Leakage Current Operating Power Supply Current Test Conditions VIN = VSS to VCC CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = V IL, VIO= VSS to VCC IIO = 0 mA, CE1#s = V IL, CE2s = WE# = VIH, V IN = V IH or V IL Cycle time = 1 s, 100% duty, IIO = 0 mA, CE1#s 0.2 V, CE2 V CC - 0.2 V, VIN 0.2 V or VIN VCC - 0.2 V Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH IOL = 2.1 mA IOH = -1.0 mA CE1#s = VIH, CE2 = VIL, Other inputs = VIH or VIL CE1#s VCC - 0.2 V, CE2 VCC - 0.2 V (CE1#s controlled) or CE2 0.2 V (CE2s controlled), CIOs = VSS or VCC, Other input = 0 ~ VCC 2.4 0.3 Min -1.0 -1.0 Typ Max 1.0 1.0 3 Unit A A mA ICC1s Average Operating Current 3 mA ICC2s VOL VOH ISB Average Operating Current Output Low Voltage Output High Voltage Standby Current (TTL) 30 0.4 mA V V mA ISB1 Standby Current (CMOS) 15 A 40 Am41DL3208G February 13, 2002 PRELIMINARY DC CHARACTERISTICS Zero-Power Flash 25 Supply Current in mA 20 15 10 5 0 0 500 1000 1500 2000 Time in ns 2500 3000 3500 4000 Note: Addresses are switching at 1 MHz Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 12 3.3 V 10 2.7 V 8 Supply Current in mA 6 4 2 0 1 Note: T = 25 C 2 3 Frequency in MHz Figure 10. Typical ICC1 vs. Frequency 4 5 February 13, 2002 Am41DL3208G 41 PRELIMINARY TEST CONDITIONS Table 18. 3.3 V Test Specifications 70, 85 ns Unit Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Device Under Test CL 6.2 k 2.7 k 1 TTL gate 30 5 0.0-3.0 1.5 1.5 pF ns V V V Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Note: Diodes are IN3064 or equivalent Output timing measurement reference levels Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS KS000010-PAL 3.0 V 0.0 V Input 1.5 V Measurement Level 1.5 V Output Figure 12. Input Waveforms and Measurement Levels 42 Am41DL3208G February 13, 2002 PRELIMINARY AC CHARACTERISTICS SRAM CE#s Timing Parameter Test Setup JEDEC -- Std tCCR Description CE#s Recover Time -- Min 0 ns All Speeds Unit CE#f tCCR CE1#s tCCR tCCR CE2s tCCR Figure 13. Timing Diagram for Alternating Between SRAM to Flash February 13, 2002 Am41DL3208G 43 PRELIMINARY AC CHARACTERISTICS Flash Read-Only Operations Parameter Test Setup JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std tRC tACC tCE tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Read Output Enable Hold Time Toggle and (Note 1) Data# Polling CE#f, OE# = VIL OE# = VIL Min Max Max Max Max Max Min Min Min 70 70 70 70 30 16 16 0 0 10 85 85 85 85 40 ns ns ns ns ns ns ns ns ns Speed Options Unit tOEH Notes: 1. Not 100% tested. 2. See Figure 11 and Table 18 for test specifications. tRC Addresses CE#f tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF Addresses Stable tACC 0V Figure 14. Read Operation Timings 44 Am41DL3208G February 13, 2002 PRELIMINARY AC CHARACTERISTICS Hardware Reset (RESET#) Parameter Description JEDEC Std tReady tReady tRP tRH tRPD tRB RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min 20 500 500 50 20 0 s ns ns ns s ns All Speeds Unit Note: Not 100% tested. RY/BY# CE#f, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#f, OE# RESET# tRP Figure 15. Reset Timings February 13, 2002 Am41DL3208G 45 PRELIMINARY AC CHARACTERISTICS Flash Word/Byte Configuration (CIOf) Parameter JEDEC Std tELFL/t ELFH tFLQZ tFHQV Description CE#f to CIOf Switching Low or High CIOf Switching Low to Output HIGH Z CIOf Switching High to Output Active Max Max Min 70 Speed Options Unit 70 5 16 85 85 ns ns ns CE#f OE# CIOf tELFL DQ0-DQ14 CIOf Switching from word to byte mode Data Output (DQ0-DQ14) Data Output (DQ0-DQ7) Address Input DQ15/A-1 DQ15 Output tFLQZ tELFH CIOf CIOf Switching from byte to word mode DQ0-DQ14 Data Output (DQ0-DQ7) Address Input tFHQV Data Output (DQ0-DQ14) DQ15 Output DQ15/A-1 Figure 16. CE#f CIOf Timings for Read Operations The falling edge of the last WE# signal WE# CIOf tSET (tAS) tHOLD (tAH) Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 17. CIOf Timings for Write Operations 46 Am41DL3208G February 13, 2002 PRELIMINARY AC CHARACTERISTICS Flash Erase and Program Operations Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEH tOEPH tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHDL tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tSR/W tWHWH1 tWHWH1 Description Write Cycle Time (Note 1) Address Setup Time (WE# to Address) Address Setup Time to OE# or CE#f Low During Toggle Bit Polling Address Hold Time (WE# to Address) Address Hold Time From CE#f or OE# High During Toggle Bit Polling Data Setup Time Data Hold Time Read OE# Hold Time Toggle and Data# Polling Output Enable High During Toggle Bit Polling Read Recovery Time Before Write (OE# High to CE#f Low) Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time (CE#f to WE#) CE#f Setup Time (WE# to CE#f) WE# Hold Time (CE#f to WE#) CE#f Hold Time (CE#f to WE#) Write Pulse Width CE#f Pulse Width Write Pulse Width High Latency Between Read and Write Operations Byte Programming Operation (Note 2) Word Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) VCCf Setup Time (Note 1) Write Recovery Time From RY/BY# Program/Erase Valid To RY/BY# Delay Typ Typ Typ Min Min Max 7 4 0.4 50 0 90 s sec s ns ns Min Min Min Min Min Min Min Min Min Min Min Min Typ 30 30 30 0 5 s 10 20 0 0 0 0 0 0 35 35 ns ns ns ns ns ns ns ns ns ns ns ns Min Min Min Min Min Min Min Min 35 0 0 Speed Options Unit 70 70 0 15 45 0 45 85 85 ns ns ns ns ns ns ns ns tWHWH1 tWHWH2 tWHWH1 tWHWH2 tVCS tRB tBUSY Notes: 1. Not 100% tested. 2. See the "Flash Erase And Programming Performance" section for more information. February 13, 2002 Am41DL3208G 47 PRELIMINARY AC CHARACTERISTICS Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE#f tGHWL OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles) tCH A0h VCCf tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 18. Program Operation Timings VHH WP#/ACC VIL or VIH tVHH tVHH VIL or VIH Figure 19. Accelerated Program Timing Diagram 48 Am41DL3208G February 13, 2002 PRELIMINARY AC CHARACTERISTICS Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SADD 555h for chip erase Read Status Data VA tAH VA CE#f tGHWL OE# tWP WE# tCS tDS tDH Data 55h 30h 10 for Chip Erase In Progress Complete tCH tWPH tWHWH2 tBUSY RY/BY# tVCS VCCf tRB Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"). 2. These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings February 13, 2002 Am41DL3208G 49 PRELIMINARY AC CHARACTERISTICS tWC Addresses Valid PA tRC Valid RA tWC Valid PA tWC Valid PA tAH tACC CE#f tCPH tCE tOE tCP OE# tOEH tWP WE# tWPH tDS tDH Data Valid In tGHWL tDF tOH Valid Out Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle CE#f Controlled Write Cycles Figure 21. Back-to-back Read/Write Cycle Timings tRC Addresses VA tACC tCE CE#f tCH OE# tOEH WE# tOH DQ7 High Z VA VA tOE tDF Complement Complement True Valid Data High Z DQ6-DQ0 tBUSY RY/BY# Status Data Status Data True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 22. Data# Polling Timings (During Embedded Algorithms) 50 Am41DL3208G February 13, 2002 PRELIMINARY AC CHARACTERISTICS tAHT Addresses tAHT tASO CE#f tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data Valid Status tAS tCEPH tOE Valid Status Valid Status Valid Data (first read) RY/BY# (second read) (stops toggling) Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle Figure 23. Toggle Bit Timings (During Embedded Algorithms) Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to toggle DQ2 and DQ6. Figure 24. DQ2 vs. DQ6 February 13, 2002 Am41DL3208G 51 PRELIMINARY AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Parameter All Speed Options JEDEC Std tVIDR tVHH tRSP tRRB Description V ID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector/Sector Block Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector/Sector Block Unprotect Min Min Min Min 500 250 4 4 ns ns s s Unit Note: Not 100% tested. VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE#f tVIDR VID VSS, VIL, or VIH WE# tRSP RY/BY# tRRB Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram 52 Am41DL3208G February 13, 2002 PRELIMINARY AC CHARACTERISTICS VID VIH RESET# SADD, A6, A1, A0 Valid* Sector/Sector Block Protect or Unprotect Valid* Verify 40h Sector/Sector Block Protect: 150 s, Sector/Sector Block Unprotect: 15 ms Valid* Data 60h 60h Status 1 s CE#f WE# OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram February 13, 2002 Am41DL3208G 53 PRELIMINARY AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tELAX tAH tAHT tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 Description Write Cycle Time (Note 1) Address Setup Time (WE# to Address) Address Setup Time to CE#f Low During Toggle Bit Polling Address Hold Time Address Hold time from CE#f or OE# High During Toggle Bit Polling Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE#f Pulse Width CE#f Pulse Width High Programming Operation (Note 2) Byte Word Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ 30 30 5 s 7 4 0.4 s sec 35 0 0 0 0 35 Speed Options Unit 70 70 0 15 45 0 45 85 85 ns ns ns ns ns ns ns ns ns ns ns ns tWHWH1 tWHWH2 tWHWH1 tWHWH2 Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) Notes: 1. Not 100% tested. 2. See the "Flash Erase And Programming Performance" section for more information. 54 Am41DL3208G February 13, 2002 PRELIMINARY AC CHARACTERISTICS 555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE#f tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings February 13, 2002 Am41DL3208G 55 PRELIMINARY AC CHARACTERISTICS SRAM Read Cycle Parameter Symbol tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH Speed Options Description 70 Read Cycle Time Address Access Time Chip Enable to Output Output Enable Access Time LB#s, UB#s to Access Time Chip Enable (CE1#s Low and CE2s High) to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#s, LB#s Disable to High-Z Output Output Disable to High-Z Output Output Data Hold from Address Change Min Max Max Max Max Min Min Min Max Max Max Min 70 70 70 35 70 10 10 5 25 25 25 10 85 85 85 85 45 85 ns ns ns ns ns ns ns ns ns ns ns ns Unit tRC Address tOH Data Out Previous Data Valid tAA Data Valid Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL Figure 28. SRAM Read Cycle--Address Controlled 56 Am41DL3208G February 13, 2002 PRELIMINARY AC CHARACTERISTICS tRC Address tAA tCO1 tOH CS#1 CS2 tCO2 tBA tHZ UB#, LB# OE# tOLZ tBLZ tLZ tOE tBHZ tOHZ Data Valid Data Out High-Z Figure 29. Notes: 1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing. SRAM Read Cycle 2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. February 13, 2002 Am41DL3208G 57 PRELIMINARY AC CHARACTERISTICS SRAM Write Cycle Parameter Symbol tWC tCw tAS tAW tBW tWP tWR tWHZ tDW tDH tOW Speed Options Description 70 Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write UB#s, LB#s to End of Write Write Pulse Time Write Recovery Time Write to Output High-Z Max Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Min Min min 20 30 0 5 25 35 ns ns ns Min Min Min Min Min Min Min Min 0 60 60 50 0 0 ns 70 60 0 70 70 60 85 85 70 ns ns ns ns ns ns ns Unit tWC Address tCW (See Note 2) tAW CS2s UB#s, LB#s tCW (See Note 2) tBW tWP (See Note 5) tAS (See Note 4) High-Z tBW Data Out Data Undefined tDW Data Valid tWR (See Note 3) CS1#s WE# tDH High-Z tOW Data In Notes: 1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 30. SRAM Write Cycle--WE# Control 58 Am41DL3208G February 13, 2002 PRELIMINARY AC CHARACTERISTICS tWC Address tAS (See Note 2 ) tCW (See Note 3) CE1#s tAW CE2s tBW tWP (See Note 5) WE# tDW Data In tDH tWR (See Note 4) UB#s, LB#s Data Valid Data Out High-Z High-Z Notes: 1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 31. SRAM Write Cycle--CE1#s Control February 13, 2002 Am41DL3208G 59 PRELIMINARY AC CHARACTERISTICS tWC Address tCW (See Note 2) tAW CE2s UB#s, LB#s tCW (See Note 2) tBW tAS (See Note 4) tWP (See Note 5) tDW Data In tDH tWR (See Note 3) CE1#s WE# Data Valid Data Out High-Z High-Z Notes: 1. UB#s and LB#s controlled, CIOs must be high. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 32. SRAM Write Cycle--UB#s and LB#s Control 60 Am41DL3208G February 13, 2002 PRELIMINARY Flash Erase And Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Program Time Word Program Time Accelerated Byte/Word Program Time Chip Program Time (Note 3) Byte Mode Word Mode Typ (Note 1) 0.4 28 5 7 4 21 14 150 210 120 63 sec 42 Max (Note 2) 5 Unit sec sec s s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4) Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 15 and 16 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. FLASH LATCHUP CHARACTERISTICS Description Input voltage with respect to VSS on all pins except I/O pins (including OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 12.5 V VCC + 1.0 V +100 mA Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 CIN3 Description Input Capacitance Output Capacitance Control Pin Capacitance WP#/ACC Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ 11 12 14 17 Max 14 16 16 20 Unit pF pF pF pF Note: 7.Test conditions TA = 25C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Description Minimum Pattern Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years February 13, 2002 Am41DL3208G 61 PRELIMINARY SRAM DATA RETENTION Parameter Symbol VDR IDR tSDR tRDR Parameter Description VCC for Data Retention Data Retention Current Data Retention Set-Up Time Recovery Time Test Setup CS1#s VCC - 0.2 V (Note 1) VCC = 3.0 V, CE1#s VCC - 0.2 V (Note 1) See data retention waveforms 0 tRC Min 1.5 1.0 (Note 2) Typ Max 3.3 15 Unit V A ns ns Notes: 1. CE1#s VCC - 0.2 V, CE2s VCC - 0.2 V (CE1#s controlled) or CE2s 0.2 V (CE2s controlled), CIOs = VSS or VCC. 2. Typical values are not 100% tested. VCC 2.7V tSDR Data Retention Mode tRDR 2.2V VDR CE1#s GND CE1#s VCC - 0.2 V Figure 33. CE1#s Controlled Data Retention Mode Data Retention Mode VCC 2.7 V CE2s tSDR tRDR VDR 0.4 V GND CE2s < 0.2 V Figure 34. CE2s Controlled Data Retention Mode 62 Am41DL3208G February 13, 2002 PRELIMINARY PHYSICAL DIMENSIONS FLB073--73-Ball Fine-Pitch Grid Array 8 x 11.6 mm February 13, 2002 Am41DL3208G 63 PRELIMINARY REVISION SUMMARY Revision A (January 3, 2002) Initial release. Trademarks Copyright (c) 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 64 Am41DL3208G February 13, 2002 |
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